This invention relates to periodic table group III-V materials, single wafer, single metal, enhancement mode complementary n-channel and p-channel pair field-effect transistor fabrication.
The invention provides an enhancement mode p-channel field-effect complementary pair in which a single metallization step realizes the Schottky barrier gate contact and the ohmic junction source/drain contacts--a single metallization arrangement enabled in part by an unusual sequence of masking operations. The invention arises from compromise between several semiconductor device disciplines--including material growth, device metallization, and material deposition. The achieved field-effect transistor is technically and economically viable for use in digital and analog transistor applications including complementary transistor pairs in uses extending into the microwave frequency range.
Several concepts appearing in the present invention also appear in the patent and publication literature as stand-alone concepts; concepts used in a different setting or concepts combined in less than the combination contemplated in the present invention. The present invention is, however, believed to represent a novel and unobvious combination of such concepts to achieve a useful complementary pair device. The concept of using the same metal in pairs of the source, drain and gate structure of a field-effect transistor, for example appears in a certain form in transistors fabricated some years ago when the self aligned gate structure was new in the art. Examples of this same metal concept appear, for example, in the two related RCA patents of Napoli et al, U.S. Pat. No. 3,764,865 and U.S. Pat. No. 3,861,024. The ame metal concept also appears in the two related Westinghouse patents of Kim, U.S. Pat. No. 3,855,690 and U.S. pat. No. 3,943,622.
In each of these four patents, however, the disclosed transistor involves use of a common metal to connect to an already formed source/drain ohmic contact and to form the Schottky barrier gate contact. In the silicon material used in the devices of these four patents an ohmic contact is moreover achieved with the mere addition of another layer of material and does not require the alloying, annealing and other complexities often used for group III-V semiconductor device ohmic contacts. The present invention is believed distinguished over the disclosure of these older patents by it use of the same metal to actually form the gate contact as to form the source/drain contacts of the transistor. Moreover, in the present invention these source/drain contacts are achieved in a non-alloyed fashion in both the p-channel and n-channel devices of a complementary pair.
The U.S. Pat. No. 4,961,194 of S. Kuroda et al., describes gallium arsenide MESFET and HEMT devices which use the combination of non-alloyed ohmic contacts, same metal electrodes, acetone solvent removal of photoresist coatings, ion implanted device separation areas and selective etching. Although each of these features may be used in the present invention, additional practices not disclosed in the Kuroda et al. patent are also a part of the present invention and provide significant distinction over the Kuroda et al. disclosure. The Kuroda etching aluminum patent, for example, does not disclose the use of a permanent secondary mask and passivation material layer nor the use of a gate aperture recess received in a gate window as is accomplished in applicants' invention. In view of the similar areas of work and in the interest of minimizing the size of the present patent document, the contents of the S. Kuroda et al. 4,961,194 patent are hereby incorporated by reference herein.
An article published in the technical literature some years ago is also of interest with respect to the single metal utilization and is additionally of interest with respect to the use of non-alloyed ohmic contacts in a field-effect transistor. This article, "A New Fabrication Technology for AlGaAs/GaAs HEMT LSI's Using InGaAs Non-alloyed Ohmic Contacts", is authored by S. Kuroda et al., apparently the same S. Kuroda et al., as appears in the above identified U.S. Pat. No. 4,961,194, and appears at page 2196 in the Institute of Electrical and Electronic Engineers Transactions on Electron Device, Volume 36, number 10, October, 1989. This Kuroda article is in fact of an especially enlightening contrast in nature with respect to the present invention since it teaches the use of a complex etching sequence during formation of the transistor elements and the present invention avoids use of this sequence in favor of a more practical and less costly procedure.
In a somewhat related situation the technical article "All-Refractory GaAs FET Using Amorphous TiWSi.sub.x Source/Drain Metalization and Graded In.sub.x Ga.sub.1-x As Layers" authored by N. Papanicolaou which appears at page 7 in the Institute of Electrical and Electronic Engineers Electron Devices Letters, volume 15, number 1, January, 1994 discloses the use of non-alloyed ohmic contacts in a gallium arsenide field-effect transistor. The Papanicolaou article however, relates to the fabrication of a high temperature field-effect transistor device, a device having refractory metal elements and involving the use of Tungsten metal. The Papanicolaou article also presents an informative discussion of the non-alloyed ohmic contact art.
The inventors of the present invention have also found the textbook "Modern GaAs Processing Methods" authored by Ralph Williams, Artech House, of Boston and London, to be of assistance in explaining and understanding certain aspects attending the present invention including its relationship with the prior art. In the further interest of minimizing the size of the present patent document, the contents of the Ralph Williams, Artech House textbook are therefore hereby incorporated by reference herein.
Although each of these documents from the prior art may relate to an aspect of the present invention it is believed that the invention as described herein represents the first combination of the plurality of concepts and compromises necessary to achieve a successful single metal, non-alloyed contact, selective etching-achieved, and secondary mask-inclusive enhancement mode field-effect transistor complementary pair device.
Non-alloyed ohmic contacts and other features relating to the present invention are additionally disclosed in several technical articles as follows.
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[6] D. BiBitonto, W. Karpinski, K. Lubelsmeyer, D. Pandoulas, G. Pierschel, C. Rente, K. Subhani, and F. Tenbusch, "Radiation and Cryogenic Test Results with a Monolithic GaAs Preamplifier in C-HFET Technology", Nucl. Inst. Methods Phys. Res. A, vol. 350, pp. 530-537, 1994.
[7] W. Karpinski, K. Lubelsmeyer, D. Pandoulas, G. Pierschel, C. Rente, K. Subhani, and F. Tenbusch, "Characteristics of GaAs Complementary Heterojunction FETs (C-HFETs) and C-HFET Based Amplifiers Exposed to High Neutron Fluences", Nucl. Inst. Methods Phys. Res. A, vol. 361, pp. 558-567, 1995.
[8] R. Williams, Modern GaAs Processing Methods, 2nd ed., Artech House, Norwood, Mass., pp. 260-270, 1990.
[9] M. Hagio, S. Katsu, M. Kazumura, and G. Kano, "A New Self-Align Technology for GaAs Analog MMIC's", IEEE Trans. on Elect. Dev., vol. 33, no. 6, pp. 754-758, June 1986.
[10] G. C. DeSalvo, T. K. Quach, R. W. Dettmer, K. Nakano, J. K. Gillespie, G. D. Via, J. L. Ebel, and C. K. Havasy, "Simplified Ohmic and Schottky Contact Formation for Field Effect Transistors Using the Single Layer Integrated Metal Field Effect Transistor", IEEE Trans. on Semi. Manufacturing, vol. 8, pp. 314-318, 1995.
[11] C. K. Havasy, T. K. Quach, C. A. Bozada, G. C. DeSalvo, R. W. Dettmer, J. L. Ebel, K. Nakano, J. K. Gillespie, and G. D. Via, "A Highly Manufacturable 0.2 .mu.m AlGaAs/InGaAs PHEMT Fabricated Using the Single-Layer Integrated-Metal FET (SLIMFET) Process", GaAs IC Symposium Proceedings, San Diego, Calif., 29 Oct. 1 Nov. 1995, IEEE Press, Piscataway, N.J. pp. 89-92, 1995.
[12] H. Kaakani, "GaAs CHFET Overview", Personal communication between Phillips, Laboratory, Kirtland, AFB, NM and Honeywell Solid State Electronics Center, Plymouth, Minn., Feb. 1995.
[13] J. K. Abrokwah, J. H. Huang, W. Ooms, C. Shurboff, J. A. Hallmark, R. Lucero, J. Gilbert, B. Bernhardt, and G. Hanzell, "A Manufacturable Complementary GaAs Process", 1993 IEEE GaAs IC Symposium Technical Digest, IEEE Pres, Piscataway, N.J., pp. 127-130, 1993.
[14] M. Meyer, "Digital GaAs", Compound Semiconductor, vol. 2, no. 5. pp. 26-32, 1996.
[15] K. G. Merkel, C. L. A. Cerny, V. M. Bright, F. L. Schuermeyer, T. P. Monahan, R. T. Lareau, R. Kaspi, and A. K. Rai, "Improved p-channel InAlAs/GaAsSb HIGFET Using Ti/Pt/Au Ohmic Contacts to Beryllium Implanted GaAsSb", Solid State Electronics, vol. 39, pp. 179-191, 1996.
[16] K. J. Chen, T. Enoki, K. Maezawa, K. Arai, and M. Yamatoto, "High-Performance InP-Based Enhancement-Mode HEMT's Using Non-Alloyed Ohmic Contacts and Pt-Based Buried-Gate Technologies", IEEE Trans. on Elect. Dev., vol. 43, no. 2, pp. 252-257, February, 1996.
[17] J. M. Woodall et al., "Ohmic Contacts to n-GaAs Using Graded Band Gap Layers of Ga.sub.1-n In.sub.x As Grown by Molecular Beam Epitaxy" J. Vacuum Science Technology, Vol 19, number 3, September/October 1981, pp. 626.
[18] S. Kuroda et al. "HEMT with Non-alloyed Ohmic Contacts Using n.sup.+ -InGaAs Cap Layer", IEEE Electron Device Letters, Volume EDL-8, number 9, September 1987, pp 389.
[19] C. K. Peng et al., "Extremely Low Non-alloyed and Alloyed Contact Resistance Using an InAs Cap Layer on InGaAs by Molecular-Beam Epitaxy", J. Applied Physics. Volume 64, number 1, Jul. 1, 1988, pp. 429.
[20] T. Nittono et al., "Non-Alloyed Ohmic Contacts to n-GaAs Using Compositional Graded In.sub.x Ga.sub.1-x As Layers", Japanese Journal of Applied Physics, Volume 27, number 9, September 1988, pp. 1718-1722.
[21] A. Ketterson et al., "Extremely Low Contact Resistance for AlGaAs/GaAs Modulation-Doped Field-Effect Transistor Structures", J. Applied Physics. Volume 57, number 6, pp. 2305.
[22] J. Sewell, C. Bozada, "A Combined Electron Beam/Optical Lithography Process Step for the Fabrication of Sub-Half Micron-Gate-Length MMIC Chips", Fourth National Technology Transfer Conference, National Aeronautics and Space Administration, Publication Number 3249, 1993, pp. 54-59.
[23] R. Zuleeg, J. Notthoff, G. Troeger "Double-Implanted GaAs Complementary JFET's", Institute of Electrical and Electronic Engineers Electron Devices Letters, Volume EDL-5, Number 1, January, 1984, pp. 21-23; IEEEe 0741-3106/84/0100-0021$1.00.
The Item 23, R. Zuleeg, J. Notthoff, G. Troeger "Double-Implanted GaAs Complementary JFET's", article in this list is of perhaps special interest with respect to a complementary pair device; however it should be recognized that this article teaches the use of multiple metallization steps in comparison with the single metallization of the present invention.
Although each of these documents from the prior art may therefore relate to an aspect of the present invention, it is believed that the invention as described herein represents the first combination of the plurality of concepts and compromises necessary to achieve a successful single metal, non-alloyed contact, inorganic secondary mask-aided, radiation resistant, low power requirement and microwave-capable enhancement mode complementary field-effect transistor pair.
The above identified previously field and commonly assigned patent application documents are also of interest with respect to the present invention in the sense that they disclose field-effect transistors of the MESFET and related types and the fabrication of these transistors using single metallization secondary mask-inclusive processing. Notably, however, the transistors of these previously filed and commonly assigned documents are of the single transistor n-channel depletion mode type wherein electron charge carriers are utilized and, moreover, these transistors are fabricated through use of diffusion dopings in layers of the transistor rather than controlled implanted dopings in initially non-doped layers as enable the present invention.